1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to accessing a semiconductor memory device according to an address and additional access information.
2. Background of the Invention
A semiconductor memory device stores data and reads such stored data. The semiconductor memory device may be divided into a random access memory (RAM) and a read only memory (ROM). The ROM is a nonvolatile memory that retains stored data even when power is cut off. Examples of the ROM include a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), a flash memory, and the like. The RAM is a volatile memory that loses stored data when power is cut off. Examples of the RAM include a dynamic RAM (DRAM) and a static RAM (SRAM).
In general, the semiconductor memory device includes a memory cell array, a decoder, and a sense amp. The memory cell array includes a plurality of memory cells connected to word lines and bit lines. The decoder provides a respective word line voltage to a selected word line in response to an address. The sense amp reads data stored in at least one selected memory cell as indicated by the address. That is, the semiconductor memory device reads data from the at least one memory cell connected to the selected word line.
However, the semiconductor memory device sometimes unnecessarily reads data from accessing memory cells connected to the selected word line. Such unnecessary reading occurs most commonly when the semiconductor memory device is used as a branch target buffer. In general, an SRAM is used for a branch target buffer.
In a branch prediction method using the branch target buffer, an embedded processor such as an ARM processor would consume much power accessing the branch target buffer for every instruction. To overcome this defect, the processor performs branch prediction in the case of a branch command, and attempts to access the branch target buffer according to a branch prediction result. Nevertheless in the prior art, the processor accesses some portions of the branch target buffer even when a branch is predicted as not taken such that power is unnecessarily consumed. In addition, the branch prediction method of the prior art undesirably complicates control logic and increases a delay of fetch logic.
As described in the aforementioned example of the branch target buffer, the conventional semiconductor memory device always accesses at least one memory cell connected to a selected word line. Thus, the conventional semiconductor memory device outputs unnecessary data, inefficiently consuming power and time.